1. Field of the Invention
The present invention relates to a level shift circuit.
2. Description of Related Art
Heretofore, a level shift circuit that converts a voltage level of an input signal to generate an output signal is well known in the art. FIG. 6 illustrates the configuration of the circuit disclosed in Japanese Unexamined Patent Application Publication No. 2000-101403. It is assumed that the input terminal IN1 is a ground power supply voltage GND, the input terminal IN2 is an input voltage Vin, the minus voltage of the power supply voltage 1 is a negative power supply voltage BCP, and a plus side voltage is a positive power supply voltage VDD. When a value of a current flowing into a first current path composed of the transistor 2, the resistor 3, and the transistor 4 is referred to as IREF1, the current IREF1 can be represented by the following equation.
            IREF      ⁢                          ⁢      1        =                  0        -                  (                      VT            +                                                            2                  ⁢                  IREF                  ⁢                                                                          ⁢                  1                                β                                              )                -        BCP                    R        ⁢                                  ⁢        3                  β    =          μ      ⁢                          ⁢      nCox      ⁢              W        L                        W      =              channel        ⁢                                  ⁢        width              ,                  ⁢          L      =              channel        ⁢                                  ⁢        length            
Further, if β is large enough, the above equation can be represented by the following equation.
      IREF    ⁢                  ⁢    1    =                    -        VT            -      BCP              R      ⁢                          ⁢      3      
If the transistors 4 and 7 form an ideal current mirror, a gate potential of the transistor 9 can be represented by the following equation.
      Vt          E      ⁢                          ⁢      9        =      Vin    -                            R          ⁢                                          ⁢          6                          R          ⁢                                          ⁢          3                    ⁢              (                              -            VT                    -          BCP                )            
The threshold of the input voltage Vin of the transistor 9 is represented by the following equation.
                    Vt                  E          ⁢                                          ⁢          9                    -      BCP        =    VT              Vin      -                                    R            ⁢                                                  ⁢            6                                R            ⁢                                                  ⁢            3                          ⁢                  (                                    -              VT                        -            BCP                    )                    -      BCP        =    VT  
If the values of the resistors 6 and 3 are specified to be equal, the threshold in which the transistor 9 is turned on and off is;Vin=0
This value does not depend on the negative power supply voltage BCP. Accordingly, the voltage of the output terminal OUT for the input terminal IN2 is;Vout(Low)=BCP Vout(High)=VDD 
Thus a desired operation can be achieved.
FIG. 7 illustrates a circuit disclosed in Japanese Unexamined patent application Publication No. 11-238379. This circuit is capable of adjusting an internal voltage. A power supply circuit 100 includes an internal voltage adjusting unit 111, a response time adjusting unit 113, a P channel transistor T1 as a voltage conversion unit, P channel transistors T2, T3, T4, and T5, and a clock signal detection circuit 21. In this circuit, the external voltage EVcc is converted into the internal voltage IVcc, which is specified by the reference voltage Vref. Even if the internal voltage fluctuates, the internal voltage adjusting unit 111 compensates the fluctuation.
Note that the response speed of the internal voltage adjusting unit for the fluctuation of the internal voltage can be adjusted by the response speed time adjusting unit 113. In response to a clock signal CLK, the clock signal detection circuit 121 activates an N channel type transistor T12 and increases the response speed of the internal voltage adjusting unit 111.